1. Field of the Invention
This invention relates generally to semiconductor device design, and, more particularly, to a method and apparatus for specifying global abutment points in a semiconductor device having ambiguous submodule abutments.
2. Description of the Related Art
Integrated circuit devices, such as very large scale integrated (VLSI) circuits, include a plurality of submodules on a single semiconductor chip, or die, that cooperate to perform the functions of the device. Microprocessors are common devices of this type. VLSI circuit design typically involves determining the submodules that are necessary in the device and generating a high-level layout diagram, or floor plan, of the device. Subsequently, the detailed implementation of the submodules are completed within the constraints of the floor plan. Eventually, the submodules are interconnected to complete the design of the device. The electrical characteristics of the device, from a global perspective, are commonly referred to as a global interconnect model. The global interconnect model evaluates the resistive and capacitive (RC) characteristics of the device.
Currently, the full chip timing analysis of the global interconnect characteristics of the chip is often postponed until near the end of the design cycle. Typically, VLSI design requires a large team of chip designers that must complete the physical design of the underlying subcircuitry for each submodule before a timing analysis can be completed. The global interconnect analysis may not be completed earlier in the design process due to the inherent uncertainty (fuzziness) in the physical footprint of each submodule that occurs as the submodule designs progress to completion. Common extraction tools used to generate global interconnect models require that the interconnections between submodules be defined exactly. Both of the interfacing submodules must have exactly the same interface physical locations. If the interface locations do not match exactly, an error condition is generated and the submodules are not seen as being interconnected. Hence, designers have to wait until all the physical parameters of all of the submodules reach a stable and complete state (ie., nearly finished) before they can begin to analyze the timing of the global interconnect between the submodules.
Because, the global interconnect analysis is critical in predicting clock frequency, waiting until the design is finished increases business-related risks. In addition, if the global interconnect analysis uncovers problems that require changes in the underlying subcircuitry, large delays in the development of the device can result. The inability to model the global interconnect characteristics of the device has led some design teams to postpone the global interconnect timing analysis until after the chip has gone to manufacturing or to eliminate the interconnect timing analysis entirely.
The physical points where submodules interface are referred to as abutment points. Abutment points between submodules (i.e., the interconnect xe2x80x9cfootprintsxe2x80x9d) are assigned using two pins, one in each submodule, with two related, but absolutely fixed, locations (e.g. X, Y, and layer) along the edges of the submodules. These xe2x80x9cedge pinsxe2x80x9d are required to xe2x80x9ctouchxe2x80x9d for proper abutment, and such an absolute connection is required to allow commonly available parametric extraction tools to obtain an interconnect model (RC model) for the entire global interconnect. Submodules without proper abutment result in network xe2x80x9copens.xe2x80x9d The physical edge pins represent the actual physical locations where the interconnect passes from one submodule into another.
If the edge pins are assigned too early in the design cycle, the resulting thousands of fixed locations overly constrain the physical layout of the submodules. Also, maintenance of the thousands of edge pin locations and coordination of changes to them between many different submodule designers is a prohibitive design data management task that inhibits productivity. In addition, the constantly changing edge pin locations makes obtaining RC models of the global interconnect very difficult, especially during the early phases of the design cycle when many changes are occurring.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for designing a circuit having a plurality of submodules includes providing a floor plan for the circuit. The floor plan defines boundaries for each of the submodules. A component list identifying internal circuit elements of the submodules and interconnections between the internal circuit elements is provided. A plurality of global abutment points are defined for the interconnections between internal circuit elements of different submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of the boundary of a particular one of the submodules.
Another aspect of the present invention is seen in a program storage device including a floor plan database, a connectivity database, and program instructions. The floor plan database is adapted to store a floor plan of a circuit having a plurality of submodules. The floor plan defines boundaries for each of the submodules. The connectivity database is adapted to store information identifying internal circuit elements of the submodules and interconnections between the internal circuit elements. The program instructions, when executed by a computer, perform a method, the method comprising defining a plurality of global abutment points for interconnections between internal circuit elements of different submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of the boundary of a particular one of the submodules.